LIBRARY IEEE;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY h_adder IS
PORT(a,b: IN STD_LOGIC;
s,c: OUT STD_LOGIC);
END ENTITY h_adder;
ARCHITECTURE one OF h_adder IS
signal abc:std_logic_vector(1 downto 0);
BEGIN
abcs